2014

Decomposing Balsa-STGs (Working Notes)

Stanislavs Golubcovs, Walter Vogler
Technical Report, Institute of Computer Science, University of Augsburg, April 2014
2014-01

 

 

2013

STG-Based Resynthesis for Balsa Circuits

Stanislavs Golubcovs, Walter Vogler, Norman Kluge
Technical Report, Institute of Computer Science, University of Augsburg, November 2013
2013-12

 

 

2012

Interface-Automata with Error States

F. Bujtor, W. Vogler
Technical Report, 2012
2012-09

 

 

2009

Robustness of a bisimulation-type faster-than relation

K.Iltgen, W.Vogler
Technical Report, 2009
2009-08

 

 

2008

Safe Reasoning with Logic LTS

Gerald Lüttgen and Walter Vogler
Technical Report, Institute of Computer Science, University of Augsburg, 2008
2008-18

 

Time and Fairness in a Process Algebra with Non-Blocking Reading

F. Corradini, M.R. Di Berardini, W. Vogler
Technical Report, Institute of Computer Science, University of Augsburg, 2008
2008-13

 

Avoiding Irreducible CSC Conflicts by Internal Communication
Mark Schaefer, Walter Vogler, Dominic Wist and Ralf Wollowski
Application of Concurrency to System Design ACSD 2008
IEEE 2008, 3-12

 

Output-Determinacy and Asynchronous Circuit Synthesis
Victor Khomenko, Mark Schaefer, Walter Vogler
Fundamenta Informatica 88 (2008) 541 - 579

 

Liveness of a Mutex Algorithm in a Fair Process Algebra
F. Corradini, M.R. Di Berardini, W. Vogler
Technical Report, Institute of Computer Science, University of Augsburg, 2008
2008-03

 

Avoiding Irreducible CSC Conflicts by Internal Communication

Mark Schaefer, Walter Vogler, Dominic Wist and Ralf Wollowski
Technical Report, Institute of Computer Science, University of Augsburg, February 2008
2008-02

 

 

2007

Combining Decomposition and Unfolding for STG Synthesis
Victor Khomenko, Mark Schaefer
ICATPN 2007, LNCS 4546, 223 - 243

 

Output-Determinacy and Asynchronous Circuit Synthesis
Victor Khomenko, Mark Schaefer, Walter Vogler
Application of Concurrency to System Design ACSD 2007
IEEE 2007, 147-156

 

Improved Decomposition of Signal Transition Graphs
Walter Vogler, Ben Kangsah
Fundamenta Informatica 78 (2007) 161 – 197

 

Ready Simulation for Concurrency: It's Logical!

Gerald Lüttgen and Walter Vogler
Technical Report, Institute of Computer Science, University of Augsburg, 2007
2007-04

 

Performance of pipelined asynchronous systems
F. Corradini, Walter Vogler
J. Logic and Algebraic Programming 70 (2007) 201 – 221

DOI

 

Output-Determinacy and Asynchronous Circuit Synthesis

Victor Khomenko, Mark Schaefer and Walter Vogler
Technical Report, Institute of Computer Science, University of Augsburg, January 2007
2007-02

 

Combining Decomposition and Unfolding for STG Synthesis

Victor Khomenko and Mark Schaefer
Technical Report, Institute of Computer Science, University of Augsburg, January 2007
2007-01

 

 

2006

Bisimulation on speed: A unified approach

G. Lüttgen, Walter Vogler
Theor. Comp. Sci. 360 (2006) 209 – 227

DOI

 

Checking a Mutex Algorithm in a Process Algebra with Fairness
F. Corradini, M. Di Berardini, Walter Vogler
CONCUR 2006, Bonn, August 2006
Eds.: C. Baier, H. Hermanns
Springer 2006, Lect. Notes Comput. Sci. 4137, 142 – 157
Copyright by Springer, Berlin, Heidelberg

DOI

 

Fairness of Actions in System Computations

F. Corradini, M. R. Di Berardini, Walter Vogler
Acta Informatica 43 (2006) 73 – 130

DOI

 

Fairness of Components in System Computations

F. Corradini, M. R. Di Berardini, Walter Vogler
Theor. Comp. Sci. 356 (2006) 291 – 324

DOI

 

Strategies for Optimised STG Decomposition

Mark Schaefer, Walter Vogler, Ralf Wollowski, Victor Khomenko
Application of Concurrency to System Design ACSD 2006
IEEE 2006, 123 - 132

 

 

2005

Fair Testing
A. Rensink, W. Vogler
Center for Telematics and Information Technology, Univ. of Twente,CTIT Technical Report 05-64

 

Performance of Pipelined Asynchronous Systems
F. Corradini, W. Vogler
Formal Modeling and Analysis of Timed Systems
Eds.: P. Pettersson, Wang Yi
Springer 2005, Lect. Notes Comput. Sci. 3829, 242 – 257
Copyright by Springer, Berlin, Heidelberg

DOI

 

Conjunction on Processes: Ready-Tree Semantics
G. Lüttgen, W. Vogler
Department of Computer Science, University of York, Report YCS 396, 2005

 

Bisimulation on speed: lower time bounds
G. Lüttgen, Walter Vogler
RAIRO – Theoretical Informatics and Application 39 (2005) 587 – 618

DOI

 

STG Decomposition: Optimised Backtracking and Component Reduction

Mark Schaefer
Technical Report, Institute of Computer Science, University of Augsburg, 2005
2005-13

 

Determinate STG Decomposition of Marked Graphs

Mark Schaefer, Walter Vogler, Petr Jančar
Applications and Theory of Petri Nets 2005, Miami, Juni 2005
Eds.: G. Ciardo, P. Darondeau
Springer 2005, Lect. Notes Comput. Sci. 3536, 365 – 384
Copyright by Springer

 

Improved Decomposition of STGs

Walter Vogler, Ben Kangsah
Application of Concurrency to System Design ACSD 2005, St. Malo, Juni 2005
Eds.: J. Desel, Y. Watanabe
IEEE 2005, 244 – 253
Copyright by IEEE

 

Component Refinement and CSC Solving for STG Decomposition

Mark Schaefer, Walter Vogler
FOSSACS 2005, Edinburgh, April 2005
Ed.: V. Sassone
Springer 2005, Lect. Notes Comput. Sci. 3441, 348 – 363
Copyright by Springer

 

Bisimulation on Speed: A Unified Approach
G. Lüttgen, W. Vogler
Foundations of Software Science and Computational Structures, FOSSACS 05
Eds.: V. Sassone
Springer 2005, Lect. Notes Comput. Sci. 3441, 79 – 94
Copyright by Springer, Berlin, Heidelberg

DOI

 

Measuring the Performance of Asynchronous Systems with PAFAS
F. Corradini, Walter Vogler
Theor. Comp. Sci. 335 (2005) 187 – 213

DOI

 

Fairness of Components in System Computations

F. Corradini, M.R. Di Berardini, W. Vogler
Technical Report, Institute of Computer Science, University of Augsburg, 2005
2005-03

 

Fairness of Actions in System Computations

F. Corradini, M.R. Di Berardini, W. Vogler
Technical Report, Institute of Computer Science, University of Augsburg, 2005
2005-02

 

 

2004

Timed Petri Nets: Efficiency of Asynchronous Systems
Elmar Bihler, Walter Vogler
Formal Methods for the Design of Real-Time Systems
Eds.:M. Bernardo, F. Corradini
Springer 2004, Lect. Notes Comput. Sci. 3185, 25 – 58
Copyright by Springer, Berlin, Heidelberg

DOI

 

Fairness of Components in System Computations
F. Corradini, M. Di Berardini, Walter Vogler
Proceedings of the 11th International Workshop on Expressiveness in Concurrency (EXPRESS 2004)
Electronic Notes in Computer Science 128 (2005) 35-52

DOI

 

Faster Asynchronous Systems
Walter Vogler
Inf. & Computation 184 (2003) 311 – 342

DOI

 

Bisimulation on Speed: Worst-Case Efficiency
G. Lüttgen, Walter Vogler
Inf. & Computation 191 (2004) 105 – 144

DOI

 

Bisimulation on Speed: Lower Time Bounds
G. Lüttgen, W. Vogler
Foundations of Software Science and Computational Structures, FOSSACS 04
Ed.: I. Walukiewicz
Springer 2004, Lect. Notes Comput. Sci. 2987, 333 – 347
Copyright by Springer, Berlin, Heidelberg

DOI

 

Bisimulation on Speed: A Unified Approach

Gerald Lüttgen, Walter Vogler
Technical Report, Institute of Computer Science, University of Augsburg, 2004
2004-15

 

Component Refinement and CSC Solving for STG Decomposition

Mark Schaefer, Walter Vogler
Technical Report, Institute of Computer Science, University of Augsburg, 2004
2004-13

 

Determinate STG Decomposition of Marked Graphs

Mark Schaefer, Walter Vogler
Technical Report, Institute of Computer Science, University of Augsburg, 2004
2004-12

 

Improved Decomposition of Signal Transition Graphs

Walter Vogler, Ben Kangsah
Technical Report, Institute of Computer Science, University of Augsburg, 2004
2004-08

 

Bisimulation on Speed: Lower Time Bounds

Gerald Lüttgen, Walter Vogler
Technical Report, Institute of Computer Science, University of Augsburg, 2004
2004-01

 

 

2003

Relating Fairness and Timing in Process Algebras
F. Corradini, M. Di Berardini, W. Vogler
CONCUR 2003 - Concurrency Theory
Eds.: R. Amadio, D. Lugiez
Springer 2003, Lect. Notes Comput. Sci. 2761, 446 – 460
Copyright by Springer, Berlin, Heidelberg

DOI

 

 

2002

Decomposition in asynchronous circuit design
Walter Vogler, Ralf Wollowski
Concurrency and Hardware Design. Eds.: J. Cortadella et al.
Berlin, Heidelberg: Springer 2002, Lect. Notes Comput. Sci. 2549, 152 – 190

 

Decomposition in asynchronous circuit design
Walter Vogler, Ralf Wollowski
FSTTCS 2002: Foundations of Software Technology and Theoretical Computer Science, Kanpur
Dezember 2002. Eds.: M. Agrawal, A. Seth.
Berlin, Heidelberg: Springer 2002, Lect. Notes Comput. Sci. 2556, 336–347

 

Comparing the Worst-Case Efficiency of Asynchronous Systems with PAFAS

F. Corradini, W. Vogler, L. Jenner
Acta Informatica 38 (2002) 735 – 792

DOI

 

Decomposition in Asynchronous Circuit Design

W. Vogler, R. Wollowski
Technical Report, Institute of Computer Science, University of Augsburg, 2002
2002-05

 

Measuring the Performance of Asynchronous Systems with PAFAS

F. Corradini, W. Vogler
Technical Report, Institute of Computer Science, University of Augsburg, 2002
2002-04

 

 

2001

Partial S-Invariants for the Verification of Infinite Systems Families

Walter Vogler
Technical Report, Institute of Computer Science, University of Augsburg, 2001
2001-04

 

 

2000

Comparing the Worst-Case Efficiency of Asynchronous Systems with PAFAS

Flavio Corradini, Walter Vogler, Lars Jenner
Technical Report, Institute of Computer Science, University of Augsburg, 2000
2000-06

 

Axiomatizing a Fragment of PAFAS

Walter Vogler, Lars Jenner
Technical Report, Institute of Computer Science, University of Augsburg, 2000
2000-01

 

 

1999

Efficiency of Asynchronous Systems That Communicate Asynchronously

Walter Vogler
Technical Report, Institute of Computer Science, University of Augsburg, 1999
1999-06

 

 

1998

Concurrent Implementation of Asynchronous Transition Systems

Walter Vogler
Technical Report, Institute of Computer Science, University of Augsburg, 1998
1998-05

 

Further Studies on Timed Testing of Concurrent Systems

Lars Jenner
Technical Report, Institute of Computer Science, University of Augsburg, 1998
1998-04

 

Comparing the Efficiency of Asynchronous Systems

Lars Jenner, Walter Vogler
Technical Report, Institute of Computer Science, University of Augsburg, 1998
1998-03

 

 

1997

Partial Order Semantics and Read Arcs

Walter Vogler
Technical Report, Institute of Computer Science, University of Augsburg, 1997
1997-01

 

 

1996

Modular Construction of Fast Asynchronous Systems

Lars Jenner
Technical Report, Institute of Computer Science, University of Augsburg, 1996
1996-02